Run simulation
Compile and run a small design. View the design and testbench below, then run. Click any step to see its output.
Design & testbench (before run)
module adder (
input clk,
input [7:0] a,
input [7:0] b,
output reg [8:0] c
);
always @ (posedge clk) begin
c <= a + b;
end
endmodule
interface adder_if(
output bit clk,
output reg [7:0] a, b,
input [8:0] c
);
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Step output
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Find the bug
Simulate a buggy design. View the DUT and testbench below, then run. Click any step to see what happens at that stage.
DUT & testbench (before run)
module adder(
input logic [7:0] a,
input logic [7:0] b,
output logic [7:0] y
);
assign y = a - b; // bug: should be a + b
endmodule
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Step output
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